Is it true that quantum tunnelling is not a problem in shrinking further the transistor but mainly the photolithography is the problem in shrinking further the transistor?
Is it true that quantum tunnelling is not a problem in shrinking further the transistor but mainly the photolithography...
Oliver Reyes
Julian Bailey
yes
Leo Long
why?
Liam Parker
No
Chase Perez
i think you're wrong
Leo Moore
en.wikipedia.org
Effectively to shine light though the photomask (but we're dealing with X-Rays no normal every day light). You have to do dozens of exposures to the same mask. Now you have to keep a mask aligned to 10nm for 100+ exposures. Good Luck
Leo Cox
Also every feature mask after that also has to keep the same alignment. Also every single waffer.
Gates do keep getting smaller. Gate size is just related to power efficiency.
Tunneling mainly effects neighboring gates. This is why you see processes that are ~14nm but only have 8% more transistors then 20nm. You can pack 14nm as densely as 20nm.
Tunnelling really hasn't effected gates since FINfet. Which is ~4 years old at this point fucking Sup Forums-tards need to get off this board.
William Cox
The end result on the market though is identical. Everyone is shit in making their chips faster. It's only the GPU manufacturers that can fool us that they are making progress, when the main thing they do is to add more cores of almost the same technology.
Lucas Stewart
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Electron tunneling is a theoretical problem that may arise *if* the channel of the transistor is not sufficiently isolated. I'm assuming you made this thread because of the shitposting of one lying autist in another thread.
Basics:
A transistor consists of a gate sitting atop of a channel which is between a source and drain.
The transistor "switches" by exerting a field of electrical resistance over the channel.
Smaller process nodes create smaller transistors.
Smaller transistors have a shorter channel.
It is progressively harder for a gate to control the current from source to drain the shorter the channel is.
Eventually, theoretically, it is possible for the channel to be short enough where a gate of effective infinite length cannot stop current from flowing even when the device is off.
This is called the short channel effect.
This is called leakage current, and it is not a principle of quantum mechanics, its a basic part of electrical resistance. Electricity is leaking out of every power cable in your house right now, and its very well understood.
Now to illustrate the short channel efft:
Picture a ramp with a marble sitting on it. You want to keep this marble in place using friction. The steeper the angle of the ramp, the more friction is needed to stop the marble from freely rolling down the ramp. Eventually this ramp is a vertical 90 degrees, and at this point fighting against gravity is just a losing battle. The marble will fall straight down no matter what.
That summarizes the short channel effect.
Xavier Ramirez
However we design new types of transistors to combat this. Moving on from planar "2D" transistors we now use FinFETs, where the gate encompasses the channel to effect better control. Ultimate leakage current is considerably lower than any planar device despite having shorter channels and smaller over all transistors.
When FinFETs will no longer be sufficient for electrical control of the channel we will use transistor topologies with greater effective gating surface area. GAAs or Gate All Around devices are sort of the holy grail for conventional transistors. Its the design that has the theoretical highest control over the channel. These are also sometimes called nanowires for obvious reasons.
Complexity in lithography:
In photolithography a light source is shined through a "mask" on to a wafer covered in photo resist to mark what parts need to get washed away and filled with another material. Be it metal, insulator, or what have you. The actual wave length of this light source being shined through the masks has become a limiting factor, we're creating structures atomically smaller than the wavelength of the light. So to create these structures we're having to utilizes double patterning, where one part requires multiple exposures to get fully developed. Some processes are having to utilized triple or even quad patterning. This increase in patterning is exponentially increasing complexity, and complexity inherently drives down yields.
You may have heard talk of EUV( extreme ultraviolet) this is an emerging new light source to combat the cost and complexity of double/triple/quad patterning.
So as we continue to make smaller transistors they're becoming more complex to produce, and that is driving up costs. New process nodes are multi billion dollar investments because of these issues. If EUV reaches mass scale it'll be a huge boon for the industry, but there is still the increased complexity from more advanced transistor topologies.
Owen Price
>I'm assuming you made this thread because of the shitposting of one lying autist
As I told you there sperg, you jumped into the discussion demanding your nobel prize when the discussion was entirely at a different direction.
I clearly claimed that chips are harder to be made faster nowadays and then I casually said quantum tunneling was one of the reasons.
The fact your nobel-prize winning knowledge claims photolithography is more important is irrelevant, the point was slowdown.
Matthew Hall
When will we start isolating from that problem? When we go at 4nm will quantum tunnelling still not be a problem?
Lucas Rivera
Challenges in structures:
More complex shapes, more electrical routing, these require more masks to be used when producing a chip. As the demand for higher performance and lower power increase we're having to explore more exotic arrangements. Naturally if follows that exotic things tend to not be simple. Having a design utilize 40, 50, possibly even more masks is now becoming a reality. Every pass introduces the potential for a small flaw, and that flaw can get magnified in each successive layer. Again yields suffer. The less viable candidates per wafer the more expensive those remaining good dies are.
We've transitioned from relatively simple 2D gates, to current FinFETs, and that is the perfect case to examine some issues inherent to bulk silicon.
With bulk based structures you have a higher degree of doping required, you inherently need more masks to build up base isolation structures for critical areas of the transistor vs a device built on an SOI wafer. Each has its own set of advantages and disadvantages, but SOI structures are simpler.
The doping of the wafer itself is a vital step, and one of bulk's biggest downsides. Dopants need to be distributed with atomic level precision, a single misplaced atom can adversely impact the entire transistor built ontop of it.
youtube.com
Jose King
When process engineers talk about electron tunneling they aren't talking about simple leakage current. Leakage is just a reality of anything using electricity, its a fact of life. Electron tunneling as a problem would be errant current shooting out of one device, hitting another, and interrupting its function, which could potentially freeze a whole chip, or even kill it over time.
Moving down past 10nm, to 5nm, and 3nm, transistor topology will change accordingly. This isn't an industry where one can wait by and see if something goes wrong to address it after the fact. Devices are first built on theoretical models, then simulated in software. An entire new process node will first be modeled as a single transistor before any test chip is even close to being taped out so the behavior of a single switching gate can be checked.
Smaller process nodes will be accompanied by transistors appropriate for their size and electrostatic characteristics.
Brandon Harris
Money is the cost in further shrinking the transistor.
It costs money to buy EUL equipment.
It costs money to refit fabs.
It costs money when yields are lower.
It costs money to research alternatives.
Tyler Howard
So in summation, I guess:
The key issues facing continued area scaling are complexity in lithography, current lack of EUV(immersion is another possibility but neither are widely used yet) and the increasing complexity of structures themselves. Every node node requires more input in raw man hours which will directly translate into the cost of bringing the node online, and ramping up to production ready levels.
Ensuring that harmful electron tunneling isn't present is like Ford ensuring that their cars leave the factory with tires installed. It is a fundamental basic, not a limiting issue.
James Hill
Moore's law is dead for more than 15 years. They fooled us it isn't with the dual core. NVIDIA is getting away with it with cramming more cores and increasing the price.
Alexander Ramirez
Don't know what the latter is, but quantum tunneling is definitely a problem.
Dark silicon is also a problem. In a nutshell:
>double the amount of transistors on the die every 1.5 years or so
>have to turn off/constrict power to roughly half the chip
>to give the illusion of extra power, add more cores, which is trivial to do
Jack Green
>Murphy's law
>Murphy
Nice deleted post.
Moore's Guesstimation was never anything but. It isn't about the performance of a CPU, its about the number of transistors that we can economically put in a die. Doesn't matter if you achieve it through adding more cores, IGP, or anything else. That statement was strictly about transistor counts.
Henry Stewart
Look into Dennard Scaling. It is an actual formula/research behind why Moore's law works. It predates Moore's law itself and was the foundation for Moore's conjecture in the first place. Basically, it comes up with a clever mathematic basis for shrinking silicon, reducing power and capacitance, and increasing frequency. The catch of course is that power consumption goes up a little bit, iirc.
Asher Hernandez
This is why 775, 771, 1366, and 1567 are still worth something and will probably still being used if they work 20 years from now. Progress has gotten harder.
They should be going for higher clock rates, not smaller gates.
Noah Ramirez
you know that smaller gates directly correlate with higher clocks, right?
Owen Rivera
This isn't actually true.
Some of the fastest switching devices ever are fairy big test transistor.
IBM's 32nm PD-SOI clocks very well in production chips, better than some smaller bulk devices. The transistors used in your desktop processor are tailored to hit a certain power and frequency target. Certain variants of any process may clock significantly higher, but do so at unacceptable power levels for a consumer product. You can't make a generalized statement about characteristics of an entire process based on what you see in a consumer CPU, all you can see is that one Vth. Even then the architecture itself is an enormous contributing factor to clocks.
AMD's Vishera can clock over 8ghz on LN2.
Intel's Kaby Lake has hit north of 7ghz.
They're radically different processes, radically different architecture.
Matthew James
Quantum tunneling makes your transistors operate with worse characteristics, it's not a fabrication issue, it's the result of the scaled design.
Not being able to place photoresist properly prevents smaller structures from being etched entirely.
So what you're asking is a bit incoherent.
In general people have been expecting wavelength of the light to be the limitation for a while now (even at 0.13um or something they started claiming this I believe) but people somehow found new ways. Like masks that look nothing like the final layout, or using two masks to cancel out distortion around the edges. So lithography as we use today may not be able to go any further but lithography also changes, they'll start using different type of illumination different photoresist and other stuff probably.
Also the drive for smaller geometry is not as strong as before.
Jack Bailey
You cant focus light that far. Its a basic problem for microscopes and why we use the electron microscope.
Ayden Barnes
> Gamma ray litography
> when
Xavier White
>shoot gamma rays at something
>turn it into swiss cheese
Sebastian Cooper
>this kid is mad as fuck and got utterly BTFO
LMAOing at ur life
Anthony Reyes
Right now, it's mainly the photolithography. The current process uses light that is severalfold longer wavelength than the feature size, and shorter wavelengths have yet to be incorporated into production at scale. Quantum tunneling becomes more of an issue below 10 nm, but we still aren't there yet commercially; right now, the biggest issue is low yields with the photolithography process.
Cameron Williams
Autistic fuck, if it's deleted it's corrected so shut the fuck up narcissist cock. Second, only an autistic fuck would believe Moore's Law was designed to only talk about transistor count and not speed. Only an autist like yourself would seriously claim the propaganda wasn't to directly connect count with speed.
So shut the fuck up.
Matthew Evans
Finally, an answer from someone that doesn't act like a sperg that pretends they need a nobel prize for the buzzwords he read by googling wikipedia.
Ethan Gutierrez
Butthurt patholocial lying retard. Got caught talking out of his ass, and started crying like a baby about it.
Samefag butthurt retard.
Brayden Long
> I'm incapable to form coherent arguments so I'll just troll.
Sup Forums is the only place that will give you recognition.
Tyler Baker
No, pathological liar, I'm not trolling at all. You on the other hand are a severely mentally ill cretin who can't just pretend to be an adult and own up to the fact that you were talking out of your ass like a loud mouthed kid.
These are my posts:
They stand as is. Straight forward, factual, including sources to educate anyone with the intellect and interest to absorb the material.
I'll give you a little hint: Don't try to bluff and lie in an argument with someone actually in the EE field. No amount of whining, deflection, and otherwise childish antics will help you.
Zachary Butler
Getting pretty defensive huh you got called out on your bullshit so stop it with the damage control
Landon Smith
bump