Intel has replaced the Ringbus connectivity architecture with "Mesh" in Skylake-SP and Skylake-X...

Intel has replaced the Ringbus connectivity architecture with "Mesh" in Skylake-SP and Skylake-X, after finding Ringbus scaling weaknesses post Broadwell-EP.

"Mesh" is designed principally to be both more scalable, and have lower latency than Ringbus. Thanks to extensive interconnects, it allows for performance bottlenecks to be better circumvented, resulting in lower frequencies and voltages for the same performance. In addition, "Mesh" can allow LLCs across the CPU to be unified into a larger pool without significant performance penalties, creating shared, collective access.

>itpeernetwork.intel.com/intel-mesh-architecture-data-center/

What will be interesting to see is how much better it will be for power consumption over ringbus.

Interesting how modern silicon design is trending toward slower and less power while offering wider data channels whether it's GPUs or CPUs.

Doubts of this design decision, while it is better than the legacy ringbus, it's still something used for KNL, which meant low per node bandwidth per design, clocking it higher is less than efficient now that's it's connecting far beefier cores.

We'll see how it turns out, this was only really a problem for 20+ core CPUs.

A mesh? Like some sort of fabric?

If it allows Intel to make big Xeons to start approaching 50 cores that's all you need to know about it's efficiency. Inter-core communication speed is crucial when you start getting in to 20-30+ cores. Something this fabric attempts to do.

Yeah, it allows them far higher core counts, but silicon limitations and density gets in the way far sooner than fabric.

Yes. A linking together of some fashion.

Of course. But that's not what it is trying to address. It's trying to speed up and reduce latency. And it did it extremely well managing nearly a hundred Xeon Phi cores.

Difference is that Xeon Phi cores are far smaller and lower throughput than Skylake cores, hence the need to scale and increase clocks to compensate for far bigger bandwidth per node.

The Ringbus meme will live on, in the dark, secret corners of the world.

And in Coffee Lake, most probably.

kek, took me a second

But possibly without, say, the crippling latency of the Infinity variety.

Perhaps.. like threads. Gotta be on the lookout for something that might rip them

...

Which is irrelevant. Since infinity fabric is based on Seamicros Freedom Fabric which was designed for ARM servers ans connecting thousands of cores. Does that mean infinity fabric is somehow bad now?

If it's better than their current ringbus, who cares where it comes from?

...

>UPDATE 5/22/17 11:15 PM CT: AMD has asked us to clarify that Infinity Fabric is actually not related to any of the IP or work that AMD inherited through its ill-fated and SeaMicro acquisition.

>repurposed KNL fabric with fatter datapaths/much higher clocks to handle throughput of big dick cores
A fucking bandaid.

A lot of hardware devs are realizing that building for parallel processing with lots of simple maths, gets you far better performance for the amount of time you spend developing, over highly complex and tuned problems that take a long time to develop properly, and work best on high-clock, low-throughput stuff.

Packing a lot of stuff in big lorries that drive slow, versus having guys hand-deliver stuff on a motorcycle super-quick.

No shit, throughput always scaled and will scale better than latency.

BINGBUS MEMERS GOT A TIGHT SLAP ACROSS THE FACE BY INTEL

It's literally moar bingbus. Bingbus memes were right.

pcper got btfo repeatedly on this measurement
not to mention it's irrelevant now with OS and agesa fixes

>OS and agesa fixes
?

>160ns inter-CCX latency
>but memory latency is 70-80ns
Wut.

windows is on same level as linux for ryzen cores management

there is been 2 agesa updates fixing the memory, 3200 is standard now
3600 on more expensive boards, 4000 is possible

that cuts ccx latency by x2

where my bingbros @

rip

So they say. Until AMD starts talking about it, it was born at Seamicro. It uses the same interconnect at the CPU.

Intel fanboys have utterly vanished except for thay one tripfag.

But now we can't even talk about cool Intel shit with out you AMDfags tripping over your selves to bash Intel.

Acting like some repressed nerd who goes to his highschool reunion to hold the mean bullys head in the toilet.

everyone just a bit tired of same thing every year, things are finally moving a bit

>Intel fanboys have utterly vanished
what? no they haven't, what rock do you live under? YOU are an intel fanboy, for example. It's easy to tell because you labelled an user an "AMDfag" for making fun of the ringbus design, which is quite clearly garbage and has been garbage for years. In no way does that mean he likes AMD better.

jesus christ, I read some facebook viral bullshit about a wolf pack's leader always walking far at the back to protect the slowest wolves from attack and the weakest walk at the front to set the pace. That was utter bullshit and now you're pulling a non-sequitur directly from your ass. I just wish people like you would screw your head on a little tighter before you decide your opinion is worth anyone else's attention.

>we removed ringbus!
>we replaced it with a lot of small ringbuses

Lol. Your feelings are really wrapped up in this AMDfag. It took AMD ten years to beat the ringbus design. So let's not act like it's some pile of crap. It's just dated now that the superior more modern architecture is out.

And how fucking new are you here?

>replaced the Ringbus connectivity architecture with "Mesh" in Skylake-SP and Skylake-X
So that's why Skylake-X still gets destroyed and Zen 16 cores > Intel 18 cores

how will this affect my monero mining

the only reason intel has it on the prosumer market is because of ryzen and nothing more

Underrated

So..Hear me out here.
To pull a process from the Core located at "F1" and take it to a core located at "C3", that's going to pass through 5 "nodes" on the way. Surely this will incur massive latency penalties?

Unless they've spent a long, long time designing and testing this it will be a power hungry bug ridden mess in the first release, at the least.

Think P4's hyperthreading but across the whole damn chip.

MOAR BINGBUS

fuck, does this mean that Intel can pump out 5GHz 16 core processors?

5 clocks cycles. Still less than moving through the buffered switch.

Show proof of 4000MT/s ram on any X370 motherboard please.

Nope, their updated pentium 3's still use too much power. Plus them using toothpaste tier shit instead of soldering (or good paste) makes the situation even worse. Especially sinds their 10nm seems to be a dissaster, so they can't use a superior "node" as a crutch.

Nice try, Intel.

When will Intel stop embarrassing themselves?

>bingbus no gud, wut do?
>ELEVEN BINGBUSES!

> finding Ringbus scaling weaknesses
Yeah, "finding". If it wasn't for Ryzen, Intel would put that in its CPUs again.

BTFO'd how? Just because the latency can be decreased through overclocking doesn't mean it isn't there.

which design is better?

When KNL mesh gets the same scaling call me back.

Bottom right can communicate with bottom left using only 2 steps on the AMD design, but it has to go through 6 cores on the intel design.

>BTFO'd how?
we've been through this in april got back in time if you want details

>7.90 2 socket 8 dies scaling

> Acting like some repressed nerd who goes to his highschool reunion to hold the mean bullys head in the toilet.
Well duh. What would you expect.

If it wont't be usable on physically separated dies it won't fix yield problem.

Intel always can (and probably will) go full retard. nVIDIA already did it with 815mm^2 GPU.

Yields is just one benefit of multiple dies.
Monolithic dies can't scale into so much memory channels or I/O.

And it simply means AMD fights Intel with more silicon, and that silicon is also cheaper.

Intel - 28 cores, 44 lanes, 6 channels.
AMD - 32 cores, 128 lanes, 8 channels.

AMD has more of EVERYTHING, even if its compute performance is slightly slower, it more than makes up for it with everything else.
Them being able to use every single Zeppelin die, even the ones with only 2 cores working is just a smart economical move.

Threadribber is pretty gud l, what should we do?
Make more bingbus :DDDDDDDDD:D:D
>introducing mesh bingbus
Ebin

It's not supposed to fix the yield issue. It is supposed to improve ringbus transfers and reduce power consumption by speeding up cross die information sharing.

The post which I replied to mentioned 50 cores.

It means they can pump out 24 core Xeons that scale better than ringbus.

...

>better

An early engineering sample of an 18 core meeting meeting the performance of a 22 core predecessor?

Your point?

...

Fantastic, we dip further in to irrelevancy...

Your point?

It scales like shit.

Based on? An early engineering sample?

It's not ever leaked faggit.

ES? That's clearly a retail unit you dumb twat, else it wouldn't have the naming but some shitty OPN code

That was one of the things first leaked, well before HotChips even. Zen in the enterprise market was supposed to be big because it brought disruptive memory bandwidth(8 channels) and the multicore scaling was alleged to be very high. Socket to socket communication was supposed to surpass everything intel had.

That turned out to be exactly the case as well.

>Retail Xeon Gold the Skylake-X 18-core is just a rebrand of
>Engineering sample
Pick one and only one you retarded faggot.

You bent over AMDfags are all frothy because someone questioned your cult leader?

You are the dumb fucks presenting faulty information as though it's truth.

An 18 core Xeon gold is competing with a 24 core Xeon e5. And it's supposed to "scale like shit"?

Woo lawd

That 24c is 2S board you dumb nigger.

The only stupid faggots here are you MAD fanboys who just want to shit on Intel.

Hey look more shit that gives you a minuscule performance bump while ignoring the fact that frequency gains are flat.

Ooh a 2.7ghz cpu is competing with a 2.3ghz cpu. Who would have thunk that if you increase clock speed you need less cores for same work.

>Has no idea the pictured Xeon is a retail product
>Has no idea the Skylake-X 18-core is a rebranding of it
>Has no capacity to infer what it's sub 3,000 score means when an 1800x scores 1600 and scales at 1.99 to 16c/32t
>Shitposts anyways
How embarrassing for you.

10/10 made me laugh
here's your (You)

Intel is complete shit.