LMARV-1

LMARV-1

Instructional video series making a RISC-V processor without an FPGA

youtu.be/yLs_NRwu1Y4

Other urls found in this thread:

riscv.org/wp-content/uploads/2016/07/Tue1130celio-fusion-finalV2.pdf
en.m.wikipedia.org/wiki/IBM_z14_(microprocessor)
twitter.com/NSFWRedditGif

video does not exist, hooktube can't open it either.
WTF is going on?

Gosh you're smart

Works for me

fuck off shill

>no backdoors

trash it

that dude in vid looks like bisquit after an upgrade

really enjoyed, thanks

Convince me that RISC can even IN THEORY be better than CISC. Don't give me that "muh decode complexity" bullshit. Dense instruction coding is what's good about CISC, and modern CPUs are bottled by memory so it's pretty fucking important.

I can't, and that is not what this thread is about

>not what this thread is about
I fucking guarantee you if this thread goes on it will devolve into a heavy pedophilia flame war.

How about the fact that all current x86 processors are actually a RISC processor hiding underneath the x86 instruction set.

the only people who care about the RISC part of RISC-V are morons stuck in the ‘90s, that’s not what anyone with a brain is interested in here

Show me 1(one) modern CISC CPU.

That's pretty much the DEFINITION of a CISC machine. You think I don't know that? CPUs can only fit so much cache in them. The instruction encoding on a CISC machine is, in a way, in a neatly compressed form, and not only will you get fewer icache misses, but the reorder buffer can fit more instructions in it, and see at a higher, more pragmatic level how to reorder them.

Do you own a desktop?

the point of RISC-V is that RISC is easier to implement. Thus this has a greater chance of being implemented by many vendors with a higher success rate.

code density is not a major goal of the RISC-V project, but it manages anyway.

RISC inside.

If it is to even become remotely successful then a processor that implements it BETTER have a good enough reorder engine to plow through the crazy inane shit that ALL "optimizing" compilers puke out.

It also NEEDS good SIMD support on said processor(s).

Also please source that image for me.

You're hiding something. Tell me the name of the processor.

>hurr x86 have small risc-like code in it so it is risc durr

Go suck a fuck.

The ONLY reason CISC machines were failing badly 30-40 years ago was a mixture of poor implementation and implementing tons of esoteric instructions...poorly. A modern CISC can dispatch an instruction to the correct ALU/whatever perfectly, as it has dedicated hardware for that instruction and has a much higher level understanding of it. It doesn't have to piece together the meaning of a line of "simple" instructions to figure out what it's doing, and the dense instruction encoding of CISC eases icache memory as well.

riscv.org/wp-content/uploads/2016/07/Tue1130celio-fusion-finalV2.pdf

fuck replied to the wrong post

Here you go
en.m.wikipedia.org/wiki/IBM_z14_(microprocessor)

Compressed regular instructions yield better coding density than x86. Cores are smaller, less transistors => moar coars

Honestly fuck cores. Give me more SIMD.

this is how I imagine every Slav on csgo

slavs are literally subhuman. makes me proud to be an amerimutt

AMD Opteron A1100 Series SoC specifications:

Up to eight ARM Cortex-A57 cores with 4MB shared Level 2 and 8MB of shared Level 3 cache
2x 64-bit DDR3/DDR4 channels supporting up to 1866 MHz with ECC
2x 10Gb Ethernet network connectivity
8-lane PCI-Express® Gen 3
14 SATA-3 ports

IS this shit just vaporware/abandonware i dont see it being sold or marketed anywhere?

cry more you fucking faggot