I'm working on a project and need to find someone to help code the parts that I don't know how to do...

I'm working on a project and need to find someone to help code the parts that I don't know how to do. Where do I find people to help me?

Tech meetups, forums, IRC

Alternatively just learn it, it might not be as hard as you think.

What exactly are you trying to do that you don't know how to do?

Welcome friend! You've come to the right place. There's lots of cool hardworking people here who would love to help out a talentless ideas guy like you. I'm sure you'll get lots of helpful replies here on Sup Forums - Technology. Also don't forget to fucking kill yourself faggot.

I am trying to implement a genetic algorithm. I am already learning verilog so learning two languages simultaneously would be hard for me.

haha thanks bud, didn't say I wouldn't pay them.

What's the part you need, and what language does it need to be in?

the last thing I need is the genetic algorithm, which would be manipulating a text file which contains information analogous to the genetic information. It also needs to be able to take in a value for fitness and be able to handle make files. I have no real preference on what language, it just has to work on Linux.

Is this something for school, work, a commercial project, open source, etc. I'm just curious because I'd like to know more, if possible, about what exactly it's supposed to do. What are the input data and output supposed to look like (what kind of problem are you trying to solve? genetic algorithms can be applied to many problems)? And where does verilog come in?

Its just something I have been interested in for awhile and decided to see if I could do it. The output data is technically a .asc file with text in it describing the configuration of a programmable logic device. The input is just the fitness in the form of a decimal equivalent of a percentage, the verilog is what actually is scoring and calculating the fitness.

Why is it supposed to be able to "handle make files"? If the program can process the data, why does it matter how it's built?

the way the information is sent to the programmable logic is through the use of a make file. So in order to automate this process ideally the genetic algorithm would be able to send the information to the programmable logic once it is done manipulating the genetic information held in the text file.

You need a program to read and handle genetic information, complete with fitness value, and handle makefiles? I suggest putting together an informal spec for what you need since that combination seems ludicrous from the outside.

can you clarify on what you mean by "informal spec"? Also if you have any specific questions I would be more than happy to answer them.

Not him but 1-3 paragraphs describing how data flows through this entire system and what each part does would be good.

Every program starts with "This is what I have and this is what I want to make from it."
You say in that make files are used to pass information to the programmable logic. If you want someone to take a text file full of information and the fitness value as input and output a make file, you'll need to specify the input's format and meaning as well as a mapping to the output required before anyone could even begin to start writing something.

So it would start by reading in the fitness, which is in the form of a decimal equivalent of a percentage. The better the programmable logic does at its task, the closer the fitness is to 1.0 or 100 percent accuracy. The program looks at the fitness and compares it to the highest fitness yet acheived, if its better than that configuration becomes the best, otherwise it trashes the configuration that does worse and goes back to the best one yet. It then mutates the current best configuration by randomly changing some percentage of the genetic information. Once the file has been modified, it is then loaded to the programmable logic by activating a pre-made make file which does all the steps necessary in order to program the device with the new configuration. The program then waits until the fitness is updated and continues this process until a specified fitness level is acheived.

the make file is completely done already, all the program has to do is execute it. The input is the fitness, the output is the text file. I can give you an example of the text file itself if you are interested, and the fitness is a decimal.

So the FPGA is responsible for calculating the fitness value?

correct, the fpga is what sends and recieves all information from the programmable logic, it also calculates the fitness and decides which tests to run. But I have already finished this aspect, only need to deal with the software component.

Just curious but why couldn't you do the fitness calculations in software?

I guess I could but I know way more about verilog and fpgas and hardware than software, so even though its a pain in the ass I'm trying to keep the stuff I need to port out to a minimum.

So, I read this as well. If you're reprogramming the programmable device every iteration of a genetic algorithm, stop for a moment and ask yourself why.
That aside, what I hear you saying is that you need to compare a given value to the historical maximum for that value, use the result of that comparison to select an input file, structure unknown to me, and make random changes to that file, before both saving a copy of it for later use, and writing it to a file name known to the make system before invoking make.
Look at scripting languages like Python, which is relatively easy to pick up, to do this automation task.

work with a local cs department and make someone do it as their senior project for free

I have purposefully not explained the overarching purpose of my project for personal reasons, but I have a very clear goal in mind. You definitely understand what im going for and I appreciate the feedback, I will look into python immediately. Also if you want I can send you a copy of the file that encodes the genetic information if you have further interest.

I wish, I already work full time with hardware so that might be tricky.

>encodes genetic information

lol, the shit that comes up on Sup Forums

if you want me to explain more I would be happy too, but in the context of a genetic algorithm it can be useful to explain mechanism in a similar scope as real genetics.

It might actually be easier to just redo the whole thing in software. How complicated is the fitness calculation routine anyways?

To do it the way you're planning, you'd need to write some kind of driver to communicate with the FPGA over USB, which can be a pain.

Alternatively you could get one of those UART to USB thingys, add a UART interface to the FPGA so it can send the fitness value, then have the program listen on the appropriate device file in /dev/ to get the fitness value. You can probably also use this UART interface to send the updated text file to the FPGA so you don't have to reprogram it every time, just update whatever structure in the FPGA is holding the data.

I agree, but that is really out of my scope and I would have to hire someone to help. The fitness calculation is only as complex as the task being tested which for what I have ranges from a counter to complex rules. So there are open source USB modules for FPGAs and some FPGAs come with these in order to program them. But in order to map a new structure to an FPGA the information has to go through a synthesizer and a place and route program, the way I am doing it does cut out on the synthesizer but a place and route is mandatory in this case.

Exploiting summer interns is a traditional part of practically every engineering discipline, user.
I'm currently 8 beers into a holiday six pack so the last thing you want is me doing on-the-fly system design. I have to deal with FPGA's done in Verilog or VHDL at work, even though I'm the software guy. Trust me, if you can keep that nonsense straight, you can automate your system yourself. The best advice I can give is to work out how you'd do it manually with sheets of paper, then automate that process.

You'll also need to write a driver for Linux. Expect to pay a lot to get the sort of person who can do that.

Get out normie

My only worry is that the time it would take me to do everything may start to become too much for me to handle while working full time. But I see it moving more toward this scenario the more I learn. Also cheers currently enjoying some beer myself.

I am fairly lucky in that there is a boat load of open source fpga stuff for linux that I have been using the shit out of so I think I might be set in that regard.

Now you've got me thinking, you poor bastard. Is the actual calculation of fitness changing each iteration, or just the inputs to the calculation?

haha, just the inputs. But the kicker is that multiple tasks can be run one after another and a total weighted fitness of all the tasks is calculated, can get interesting.

also just for reference if anyone here is interested enough to talk more and this thread gets deleted I'm going to leave a burner email.
[email protected]

This comes back around to my initial thought, why reprogram every iteration? Can you store the candidate for evaluation in addressable, re-writable, on-device RAM?

Some FPGAs do have the ability to store multiple bitstreams and implement them based off of verilog programming, also the file size for a smallish bitstream is about 200 kb so the device has to have enough memory which isn't usually a problem, but the device I am using has nowhere near this amount of dynamic memory. And unfortunately I have to use this type of FPGA because of an open source toolchain that is paramount to this project.

>processing text files with Verizon
that's the most retarded shit I've read on Sup Forums.

uhhh what, I never said anything about verizon.

I'm in software for power electronics, so to me FPGA's are for tasks that need to be done in parallel, at high speed, and independent of my control code. Is your evaluation function making use of massive parallelization? I ask since reprogramming every iteration is going to swamp any speed-up one might see from executing the evaluation in hardware.

So my verilog is parallel in the way that each task is run on its own logic path in the FPGA, but because of the nature of what I'm trying to train in the programmable logic, parallelization is not beneficial. More accurately, training something to do serial tasks is way easier than training something to do parallel tasks. As for speed I absolutely expect this thing to run for days and days before reaching applicable fitness levels.

Is this FPGA doing any I/O with the outside world during the evaluation? Honestly, it doesn't sound like you're using it for what it's good at doing. The people saying to re-implement it all in software may be on to something.

So just to make this clear there are 3 physical elements being manipulated here. There is the programmable logic being manipulated by the genetic algorithm which runs on a linux laptop, and then there is an FPGA which stimulates and reads from the programmable logic and calculates the fitness. So the FPGA is connected with the computer via USB and the programmable logic via PMOD connectors, and the programmable logic is also connected to the laptop for uploading new configs. And I agree that re-implementation is a good idea if I had the programming skills, or

or I had a shit load of time, which unfortunately I do not. So hiring someone would be my only avenue.

If you pay me I will make this for you.

Okay, what I think you have. The FPGA code changes infrequently, if at all. The PLD code changes every iteration of your GA. One iteration consists of getting a fitness value for the current PLD code from the FPGA, comparing it to previous results to select a new base PLD code set, modifying the selected base to create a new PLD code set, reprogramming the PLD, and then initiating a new fitness test. Iterations halt when the fitness value meets or exceeds a target value.
If I'm even close and if you could already do all this from the command line (except for editing the base PLD code, which would need an editor), than you can automate this using a scripting language like Python as the glue to replace your fingers at the keyboard.
Modifying the code for the PLD could be easy, hard, or anywhere in between, since I've no idea how it's coded, or what modifications would require.

how much

Right on. The FPGA code is based off of the tasks you want to train, so pretty infrequently. PLD configuration is changed every cycle, because the quicker you can run iterations the quicker it can improve. The PLD code is a text(.asc) file that uses ones and zeros to control every possible configurable bit on the device with some text in between. I can send you the file to check out what kind of structure it has if you want.

I haven't really read the thread, but we use a pretty expensive FPGA machine at my university for working on stuff like evolutionary algorithms where the parallellism allows you to run a massive amount of individuals in parallel

verilog is very close to C, but I would probably use C++ for the genetic algorithm.
I wrote one last semester using the eigen library for the neural network.
If you are writing it in hardware, the hard part is the random number generator and an easy way to do matrix multiplication.

Alright so i'm going to bed now but I appreciate all your responses. If anyone is interested in talking more I have included a burner email just incase this thread gets deleted, its [email protected]. keep on rocking.

GGS

We're getting there. You have two things to create: the supervisor code that runs the training process described here and the program that permutes the PLD code. The first you should be able to do on your own with a bit of exposure to a scripting language, since most if not all are able to build a command line and execute it. The second is the one you could farm out, but only after you work out what you want to have happen to the PLD program. Don't try to hire someone to do it until you can sit down with a PLD file and a text editor and modify it yourself. At that point you can write the informal spec. Even better, at that point you may realize you can write the program yourself.

alright awesome, thanks for the help. I'd love to talk more if you have the time, but I gotta catch some sleep. I posted my email in this thread a couple times so if this thread gets pruned, message me if your interested.