What does Sup Forums think of AMD Zen...

What does Sup Forums think of AMD Zen? its ocming out in a month and supposedly it competes with the best intel processors.
i hope its good so i can buy one and then write a letter to intel saying i wont buy from them because they are a SJW company

Other urls found in this thread:

hardforum.com/threads/intels-unveils-7th-gen-intel-core-processor.1909469/
anandtech.com/bench/product/1684?vs=288
anandtech.com/show/10591/amd-zen-microarchiture-part-2-extracting-instructionlevel-parallelism
anandtech.com/show/10591/amd-zen-microarchiture-part-2-extracting-instructionlevel-parallelism/5
twitter.com/SFWRedditGifs

My Mobo is ready

>its ocming out in a month
you mean 8-10 months or 244 days - 305 days or 5868 - 7320 hours or 352080 - 439200 minutes or 21124800 - 26352000 seconds


enjoy the wait, for the wait will be long

rumors are that there is a limited release in october

AMD is such a piece of shit that not even zen will save it. Sandy bridge level of performance in 2016 LOL. I'll stick with quality, I'll stick with Intel.

The key word there is limited. I certainly doubt AMD will magic up enough of a supply for the common pleb (let alone motherboard manufacturers doing a run for this supposed limited release).

AM4 boards and Bristol Ridge (Excavator, i.e NOT ZEN) APU's get released then, not Zen.

It's shit because it includes AMD's Platform Security Processor, which like Intel's Management Engine is a US court ruling away from being a hardware back door.

It's only 1 backdoor.
Intel has numerous and Kaby Lake will have a hardware DRM protection too.

I will enjoy the price drop on i7s that zen will bring

And buy a i7 anyway

> Kaby Lake will have a hardware DRM protection too.

I just read about that...Intel is digging their own grave, everyone pirates
this will only drive people to use AMD cpu's

(I wish that was the case, the general populace is pretty dumb)

Getting real tired of AMD fanboys gushing over how amazing Zen is. Wait for fucking benchmarks, Jesus. Does anyone remember Piledriver?

>Intel has numerous
Source?

>a hardware DRM protection too.
Are you talking for videos and shit? If so they've been doing it for a while now with code that runs in the IME and I'm pretty sure AMD already does it with similar code running in their PSP. Everything is shit now days.

>let alone motherboard manufacturers doing a run for this supposed limited release
See Same motherboard for both. Zen probably won't be very available until January sometime but the motherboards will have hit the market long before then.

>This video engine also enforces anti-piracy DRM protections as required by the major studios. Hollywood bosses didn't want to stream 4K ultra high-def content from online clouds without mechanisms in place to thwart casual rippers, and so Intel gave the entertainment giants what they wanted.

>"There are hardware-based protection mechanisms to make the studios comfortable with sharing high-quality content to PCs for the first time," said Regis.

source: hardforum.com/threads/intels-unveils-7th-gen-intel-core-processor.1909469/

Intel's processors have supported HDCP for a while now, they're just rolling out support for the newest version of HDCP (which it is possible that they could backport it to their older processors). HDCP on all Intel processors runs in Intel's IME, there is nothing special about this new processor. As for AMD, their GPUs have supported HDCP for years now so it's extremely unlikely that they wouldn't implement HDCP 2.2 compatibility for their new processors. Welcome to the cyberpunk world of today where all new hardware development is controlled by corporations who want to squeeze as much money out of you as possible.

No, there is no rumor about limited release in October. AMD's slide deck that got leaked last marched has October slated for "IP." That means final silicon is in production, not that its available to anyone.
AMD will probably ship some chips to OEMs in December, and they won't be available to purchase on the builder market until January or later.

That being said it'll show an average 40% IPC uplift over Excavator.
Thats more than a 60% uplift in IPC over Piledriver.
The design has no CMT penalty to multicore scaling will be significantly higher.
SMT increases throughput per core with no penalty aside from die area and transistors.
In well threaded workloads 8c/16 Summit Ridge should provide twice the throughput of 4m/8t Vishera. In things like Handbrake AMD should be competing against the top end of Haswell-E.

Piledriver is exactly what AMD said it would be.
Bulldozer is exactly what AMD said it would be.

Only fanboys read into statements and give themselves absolutely unrealistic expectations.

>its ocming out in a month and supposedly it competes with the best intel processors.

zen isn't until q1 2017 and it won't be competing with intel's latest CPUs. at best it will compete with sandy bridge, which will be 6 years old by then.

so how does it compare to intel?

>SMT increases throughput per core with no penalty aside from die area and transistors.

SMT is not free. You're sacrificing perf/watt to get that extra throughput, even Intel's implementation that they've had a decade to perfect still turns CPUs into housefires.

This, Intel already has HDCP 2.2 support updates for chipsets that support IME version 8 going back to 2012 (starting with firmware version 8.1.65.1568). This isn't some new thing and it wouldn't surprise me if AMD's Zen processors support it as well.

Its Excavator with a 40% IPC uplift, and no CMT penalty.
This is Excavator vs Sandy Bridge: anandtech.com/bench/product/1684?vs=288

Excluding the particularly FPU heavy workloads Excavator isn't that far behind.
Handbrake, X264 bench, 7zip MIPS bench, POV-Ray, Cinebench R10 and 11.5, Excavator with 40% higher IPC would be competitive here core per core.
Zen will probably land around Ivy Bridge in average perf/clock, do better in some metrics, and worse in others because they still don't have an enormous FPU with wide data paths like intel does.


90% of SMT utilizes resources already in the core, those transistors spent on its dedicated hardware barely pull any power. Take an i7 and measure its power draw at load. Now disable HT in BIOS and do the same.
The difference is a couple of watts.

Where did you get one?

>90% of SMT utilizes resources already in the core, those transistors spent on its dedicated hardware barely pull any power. Take an i7 and measure its power draw at load. Now disable HT in BIOS and do the same.
>The difference is a couple of watts.

learn how SMT works before you shitpost. keeping parts of the core utilized that would otherwise be idle and unpowered when the CPU is stalled at some other stage definitely degrades perf/watt, you're losing something like 30-40% perf/watt on any modern intel cpu for a 20% perf gain in big workloads.

top kek AMDead shill everyone knows that zen is hot garbage, 14lpp being chink dogshit will destroy any potential it has

you forgot your ®'s Pajeet, I'm going to have to dock 3 rupees from your next paycheck.

>I have literally no idea what I'm talking about: The post
Its like you've never looked at a single review in your entire tech illiterate Sup Forumsirgin retard life. The difference in power delta between an i5 and i7 at equal clocks is only a couple of watts, and this includes the i7 having more cache active.

You're just talking out of your ass like a clueless underage kid.

>The difference in power delta between an i5 and i7 at equal clocks is only a couple of watts, and this includes the i7 having more cache active.

maybe if you keep the same clocks and voltage, but HT on every intel uarch since sandy bridge usually needs extra voltage and lower clock speed to keep the CPU stable. i've seen 2600k's that could do 5ghz at 1.325v with HT disable, then couldn't even do 4.7 at 1.4v with HT enabled.

Obsolete.
Laugh at it while there's still time.

You should read up on Power8's SMT implementation. Two of the engineers AMD brought over for Zen's development were part of that IBM team.

That's even worse because POWER8's SMT implementation is more analogous to CMT (excess/shared resources packed into one core) than 'true' SMT (utilizing parts of the core that are idle when one thread is bottlenecked elsewhere).

All SMT shares certain parts of the core.
Stop trying to talk about things you don't understand.

the key word was 'excess'.

I'll buy it if it's better value for money for what I need than intel.

If you have used anything but intel in the last 10 years you are basically retarded

>That's even worse
Debatable. Power8's SMT implementation allows each core to use less power than a single Intel core for similar multithreaded performance. It is also said that Zen (or K12) may feature the variation of Power8's design that can further split each core into multiple threads for up to four threads per core, OR can share threads between two or more cores if demand allows.

>phenom 2

Zen most definitely isn't emplying SMT4, they most certainly aren't going to employ crazy clustered execution like VISC either.
The only practical examples of CSMT in the world are low clocked stuff created in FPGAs for academic study, or VISC's chips which are still very much in development.

AMD did say that they were working on a design inspired by VISC for a future product. Whether it's K12 or Zen or even this coming generation, I don't know. They are a major backer in the VISC project, so it stands to reason that they're working towards making VISC-like features (like the shared threads) a reality.

>the return of the reverse-hyperthreading meme

Back in like 2005~ AMD had a patent showing they were working on something similar. Companies however patent all kinds of impractical things they'll never use just so they can hold on to it for legal leverage.

It would be completely revolutionary if anyone actually got the concept to work to a degree usable in a consumer product without running at absurdly low frequencies or with horrid latency.

I'm fairly certain Zen will have an SMT feature that's more inline with Power8's design than Intel's. You don't poach brains at the start of a project and never put them to use.

However,
SINGLE
MEMORY
CHANNEL
PER
CLUSTER
Zen will be shit compared to all modern Intel CPUs in memory and cache performance. Count on that.

the only real tactic

unless the zen actually proves itself worthy

anandtech.com/show/10591/amd-zen-microarchiture-part-2-extracting-instructionlevel-parallelism
>These two 8 MB caches are separate, so act as a last-level cache per 4-core module with the appropriate hooks into the other L3 to determine if data is needed.

anandtech.com/show/10591/amd-zen-microarchiture-part-2-extracting-instructionlevel-parallelism/5
>This means that the true LLC for the entire chip is actually DRAM, although AMD states that the two CCXes can communicate with each other through the custom fabric which connects both the complexes, the memory controller, the IO, the PCIe lanes etc.

Stop regurgitating baseless bullshit already disproven.
The L3 is not isolated to a single CCX, they can all communicate. The memory channels sure as fuck aren't isolated either. This is the most laughably clueless tech illiterate FUD bullshit I've ever seen. Where the memory PHY are oriented on the die do not tell you how they're connected to anything.
Both memory PHY are connected on the BEOL to the IMC. The IMC is what interfaces with the core. There aren't two IMCs, and the IMC isn't arbitrarily partitioning memory between them.
AMD made it very clear that they have a coherent fabric connecting everything together that facilitates their scaling into MCMs. Isolated CCXs in a 4 die MCM would be pointless.

You're mindlessly regurgitating bullshit from Anandtech forum trolls. Quit spreading FUD or go slit your wrists open, kid.

Looks like the AIDF showed up again.
Desperate to cash in those AMD shekels, aren't you?

top kek dumb AMDrone not realizing that '''fabric''' is just a fancy word for saying 'hundreds of microseconds in latency'.

14LPP's poor performance and AMD's terrible '''modular''' design will come back to bite them in the ass when they finally lose the last few thousands customers they had.

>get proven wrong
>shitpost

Oh look, its the autistic NEET showing up yet again.

>Both memory PHY are connected on the BEOL to the IMC. The IMC is what interfaces with the core. There aren't two IMCs, and the IMC isn't arbitrarily partitioning memory between them.

[citation needed]

AMD would be disabling the redundant controllers if this was the case, but we already know they aren't (and the fact that they're silent about making any statement about this would indicate that it's less than ideal for the average consumer).

>autistic NEET

The things we dislike most in others are the characteristics we like least in ourselves.

>they have a coherent fabric connecting everything together that facilitates their scaling into MCMs
>trusting AMD's words
I bet you gobbled up their bullshit about how their L2$ latency got better with Excavator because they literally shaved off half of their cache size to make up for their slow, shitty library. PROTIP: their cache latencies are EXACTLY the same as Piledriver, but now you only have half the cache available to you.
MUH PROGRESS
SHILL FOR THE HIGH SCORE FOR MUH LISA SUU

nice post pajeet

>asking for a citation on the basics of how wire interconnects work
>not understanding how a memory controller works
You're beyond retarded, NEET.
Orientation of structures on the FEOL have absolutely nothing to do with BEOL connections. Do you really think that each PHY around the circumference of a GPU is only feeding the ALUs immediately surrounding it? The PHY connect to the IMC, and the IMC is wired into all logic on the die.

You're a jobless subhuman, I'm a gainfully employed CAD designer. No amount of deflection will ever change how pathetic you are, low functioning autistic NEET.
You do nothing but shitpost and spread FUD. Every single thread its the exact same thing. All of your posts are exactly the same.

It's funny to see AMDrones making shit up in order to justify their bad purchasing decisions.

protip: buy skylake now while it's available before Intel fully gimps you losers when AMD folds in 6 months after Zen is revealed to be a complete disappointment.

Going to fuel my gaming PC makeover + Vega

>I'm a gainfully employed CAD designer
So you're a bottom-feeder then?
>2016
>not running your own business

This, AMD only exists as token competition. Cucks can buy their shitty products to help the actual masterrace stay afloat.

Hopefully they drop prices of the i5s too. They probably destroy zen as well.

>limited run
>beta testers
prove me wrong

Go on. Start calling everyone with a job a "wage cuck" now.
Its all you NEETs do.

>I'm a gainfully employed CAD designer.

so you draw blocks on a screen for a living? that's a skill that every 12 year old has these days. no wonder you're poor, you're literally less skilled than a minecraft playing child.

>Orientation of structures on the FEOL have absolutely nothing to do with BEOL connections. Do you really think that each PHY around the circumference of a GPU is only feeding the ALUs immediately surrounding it? The PHY connect to the IMC, and the IMC is wired into all logic on the die.

nice autism, i'm still waiting for a source instead of your unqualified opinion and unfounded assumptions about amd's cpu designs.

A Core i3-6100TE will BTFO any Zen

No seriously, if you're so smart then why don't you own your own business. Shit is like the easiest thing to do.

GMI is per-die not per-complex you idiot. There is an IMC paired with each CCX that is linked through the GMI. One complex can probably use another's controller but would come at a big latency cost.

Cant wait for Another Massive Dissappointment :^)

reminder that literally the only thing keeping AMD afloat is buttcoin miners buying their shit in droves and inflating their sales.

let me translate this post from shill to english

>"I didn't understand any of this shit better play damage control"

Which year?

I don't think I've ever seen worse examples of the Dunning-Krueger effect in the wild.

I own my own small business and I turn a profit no matter what I do. Even when I make losses, I still turn a profit, sometimes more than what I'd earn in the same quarter. Know your place, wagecuck.

>IT
>WILL
>FLOP

GMI are the external links used to connect multiple dies together.
Connecting multiple dies together would yield no benefit if the CCXs per die could not communicate with high bandwidth and low latency.
Two independent memory channels would require an absurd amount of copying back and forth for one CCX to see what was in the other's address space. It would be a more complicated solution, and completely illogical. More so theres literally no evidence for it whatsoever, and it flies directly in the face of what AMD has said and shown about their core arch.

Its amazing how you retards take forum troll speculation as gospel so long as it paints AMD in a negative light. I wouldn't be surprised if you or one of the other childish faggots ITT was Shintai posting here.

I think it's not out yet and we have no idea how good or bad it is.

>so long as it paints AMD in a negative light
Nigga, AMD has been painting themselves in a negative light for years thanks to Bulldozer. Why should we trust them when their budget is only a tenth of that of Intel and a third of that of Nvidia, their manpower is a fraction of both Intel and Nvidia, and they have consistently failed to live up to their performance expectations and long term support (RIP DX11 users)

>hur dur housefire
>posts a processor with 95 watt TDP
>doesn't post AMD's full retard 220 watt TDP FX-9590

This. They held a very nice price/performance ratio for a good amount of time, especially if you were building any rig under ~$400. Also, getting an x2 and unlocking 1-2 cores made Phenom II a no-brainer.

Today, the ball is in Intel's court though unless you're making an utter shitrig. Even if you save in the short-run building an AMD machine today, you're gonna pay out the ass in electricity. I hope AMD does well with ZEN just to light a fire under Intel's ass for once.

>Two independent memory channels would require an absurd amount of copying back and forth for one CCX to see what was in the other's address space.

it's AMD. they will just expect everyone to write software to conform to their boneheaded design choices instead of making a CPU that is properly designed.

Zen's primary target is the enterprise market. You're sitting here insisting that they've created something(which is totally baseless) that would inordinately harm their positioning in the enterprise market.
The notion of the Summit Ridge die having two single memory channels instead of having dual channel is literally forum trolling from habitual shitposters. Its based on literally nothing. Yet here you are carrying on as if its fact.

I never stated it as fast, I said that it would be expected from AMD as they are consistently incompetent.

you again. making fursuits yet?

from the look of it, Zen is targeting multiple markets. at least that's what I got from the whole "arch scales from 4w notebook chips to 32 core server CPUs" spiel.

Thats the Raven Ridge APU that a slide showed would scale from 4w to 35w mobile SKUs. In terms of volume sold and profit margins AMD is never going to displace intel when it comes to OEM shipments for consumer laptops. Intel has too much value added on top. Sell enough intel chips and they give away steeply discounted SSDs, or flat out hand over free CPUs to manufacturers.

AMD themselves stated that they don't see desktop PCs as a significant growth market for themselves. Enterprise is their biggest potential source of new income, thats where they're focused.

I expect Zen to be sandy tier with more cores.

I guess it will be 15% slower than the current intel at better/same price and with more cores

source?

>asking for a source on a guy's predictions
Seriously?

Twice as many cores as closest Intel competitor however with about 10% less performance. So in short it will still be 5 years behind Intel on single thread performance.

Its competing against 6-8 core Haswell-E and Broadwell-E.
Summit Ridge isn't a mainstream chip. You'd be crazy to think it would compare against the less threaded and stupidly high clocked Skylake and Kaby Lake chips.

If I had to eyeball it without knowing anything I'd say it will be around the level of an old i5 for singlethreaded but also cost nearly as much and still won't be able to be clocked as high as an Intel chip
When they go for round 2 and make it cheaper, and less voltage new Intel chips will leave it behind

>Twice as many cores as closest Intel competitor however with about 10% less performance

If power draw isn't insane you can be sure as fuck such a chip would make Intel sit up and pay attention. Servers, datacentres and whatnot would lap that shit up in a heartbeat and thats where the real money is.

This is what AMD have been saying for the past decade. In the end everyone will be disappointed when they realize history will just repeat itself again. I really want AMD to bring a top notch CPU ahead of Intel at a good price point. But the last time that happened was like 16 years ago.

>its ocming out in a month
Isn't it coming out in 2017? Wtf?

Intel isn't too terribly worried about AMD's consumer offerings.
For HEDT they're still sitting in a near untouchable position. Their i7E chips carry a 140w TDP over Summit Ridge's 95w TDP, but they're targeting much higher turbo frequencies, and still have absolute FPU supremacy.

The top most enterprise SKUs is where AMD stands to actually threaten intel, though the volume these chips move is up for debate.
Intel's 24c/48t Xeon E7 8890v4 has a price tag over $7,000. Its their top billed Xeon offering more throughput in a single die than anything else they make.
AMD is offering a 4 die MCM Opteron with 32c/64t and it has 8 memory channels instead of the 4 intel provides with their Xeons.
AMD's advantage here is that they don't have to pay for the low yields of a huge monolithic die, so their profit margins could be higher than intels, or the chips could be priced lower.
A 2 socket system with 128 threads at $5000 per socket would be ridiculously compelling vs the competition.

If you weren't doing heavy FPU ops then the AMD system might just come out on top.

>This is what AMD have been saying for the past decade
No, it actually isn't.
AMD positioned their Zambezi and Vishera FX chips against mainstream i5s and i7s. Their proposition was
>Hey, we can match this i7 in certain metrics, and actually out perform the i5 in threaded stuff. Also its only $195.

They even explicitly stated that they weren't targeting the HEDT market with their BD derivatives anymore because they flat out couldn't compete there.

>Intel isn't too terribly worried about AMD's consumer offerings.

There is a reason why AMD isn't really targetting consumers aggressively with zen - its a dying market (though still worth a lot of money) and taking Intel head-on there is pointless. Mobile chips (especially with the onboard gpu advantage AMD has) are a area where AMD can entice OEMs.

As you say enterprise is where AMD will act most aggressively.

His ass got it

NOT

COMPETITIVE

I don't suppose AM4 will have AM3+ support at all

It won't. AM4 is said to use µOPGA config with 1331 pins (pins still on CPU instead of motherboard) and northbridge and southbridge integrated on the CPU. Motherboard manufacturers will like this

Competitive is a marketing term with no concrete meaning.
20% less performance at 25% less price could be considered competitive.
5% more performance at 10% more price could be competitive.

No way. AM4 is a much larger socket, way more pins. AM3+ pinout wouldn't be able to interface with it.

>not LGA
THANK YOU BASED AMD

eh well
looks like I'll be chugging along on my oldass Biostar until we get something solid then

>AM4 is a much larger socket, way more pins
Physically it should be around the size of AM3, pin diameter has been reduced and more densely packed. I'm afraid it will be shit easy to bend

>thinking an SoC design is a good thing
I bet my clitoris that Zen will have a shitty stock frequency and a pathetic sub 3.0GHz boost clock in order to maintain its alleged sub 125W TDP.

Same energy per clock as Excavator.

You missed my point. An SoC-style integrated north/southbridge smashes all the heat-generating parts into a single die package. You're not going to get anything higher than 3.5GHz out of an overclocked Zen.