LGA 3647

Did Intel go too far?

Other urls found in this thread:

anandtech.com/show/10435/assessing-ibms-power8-part-1/7
fgiesen.wordpress.com/2016/08/07/why-do-cpus-have-multiple-cache-levels/
servethehome.com/big-sockets-look-intel-lga-3647/
twitter.com/NSFWRedditVideo

>too far
Nah 6channel RAM has market demand

You know those fucking pins exist for a reason.

That's it? So puny. Where's the 12-channel RAM?

AMD's Naples will be even bigger.

This has to be photoshopped, right?


right?

Do the numbers represent pin count, or dimensions?

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FAKE

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It represents the year from which they imported their alien technology

No its not. SP4 and SP3 have less pins than LGA 3647 too.

You think this is smaller?

I don't think its smaller, I know the dimensions of each package. You could too with a quick google search if you weren't a fucking retard. The Phi is larger.

I want to put shove this cpu between my ass cheeks

That's fascinating, how about sharing it you shiteating fuckface.

What's the advantage to Intel for making this instead of two separate CPUs?

Blimey this thread is retarded, there's no 'two CPUs' in there.

They're mostly power pins for passing more current.

One of the reasons, the other is extra traces leading to the DIMMs

>twice the size of a single CPU
>twice the pins
>probably twice the cores
Eat shit, you knew what I meant. It's larger than most of the CPUs they make, so what's the advantage of one large single component rather than two separate ones with the equivalent amount of raw power?

if you mean compared to a two socket server, the biggest advantage is that you don't have to worry about keeping each thread on the processor that's actually connected to the DIMMs where its working memory is.

Plus, lots of enterprise applications are still licensed per socket.

You're asking why one V12 is better than two V6's

What's the advantage of integrating the GPU onto the die?
Multiple cores?
The memory controller?
The cache?
The FPU?

Why are you asking this absolutely retarded question? Why would Intel split a CPU into two chips that need extra resources and space to fabricate, power and cool them while being slower?

It's dumb novelty being used to hide the fact technology has stagnated, and compensate for its inherent money loss for the companies.

>making a bigger more complex die with more hardware is 'dumb novelty'

Oh God this thread.

Start
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go to cpubenchmark.net
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go to multi socket benchmarks
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pick one
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divide the score by the amount of cpus
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remember this number
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go to single core benchmarks
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find the same cpu
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find the score
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Now compare the to score number

two cpus arent cpupower*2
more like cpupower*1.5

>wasting millions on engineering and testing a larger, more expensive package and then retooling to mass-produce it for a "dumb novelty"
Yeah you don't know shit either, there are far more efficient marketing tricks than that bullshit.

So, will Intel finally join the SLI/Crossfire faggotry with their iGPU?

>LGA 3647
so this will use 3d Xpoint memristor tech, But this is the rigth path? I remember watching an HP presentation displaying their approach to memristor tech and it appeared more advanced than intel's

Well, I welcome memristor memory

That's what inevitably happens when you can no longer keep shrinking the shit.

I mean I don't claim to know how CPUs work on the inside but if it's bigger doesn't that mean you can fit more processer stuff inside it making it run faster? I literally don't see why they didn't do this earlier, having a CPU that's a little bigger Is a pretty small trade-off if you ask me

That's a big chip

Naples has 8-channel. Intel BTFO, Skylake-X DOA.

4U

it's mostly for xeon phi. the lga 3647 xeon e7 products won't benefit at all from extra pins and won't be available to normal consumers anyway. xeon e5 and hedt will be on lga 2066.

Most v12's are actually basically two inline 6's joined at an angle. Inline 6's are essentially perfectly balanced by nature with the right firing order so it's usually easiest to begin the design that way.

I realize this is irrelevant to the point you were making I just wanted to share that fun fact.

Kekz

synchronization and bookkeeping overhead is massive. Like, it's really hard to get two cores each executing their own thread to not interfere with each other, and it does hurt performance. Now with 20 cores on a single die the problem is much more aggravated. It's even harder across sockets, you can't "just connect" two sockets, there's significant delay and bandwith limitations.

pin count.

I wish cpu companies would sacrifice a little bit of size for more performance, I wouldn't mind a cpu the size of those old pentium 2 cartridges if it meant that I could get way more performance, I mean I have this huge case for gods sakes.

i don't see how that would work

More space on the die = more transistors and more heat spreading = more speed

you can't just make the die bigger
bigger transistors use more power for some reason(chips made in a smaller process(i. e. 22nm instead of 35nm use less power for some reason)
i'm guessing you can't just put more transistors on the chip due to defects reducing yield too much. i. e. a die twice as big is 3x as expensive to produce.
you can't space the various areas on the chip out more due to interconnect bandwidth & delays increasing rapidly across distance

Possibility to pass a pointer (8 bytes) to 1TB datasets between cpu and gpu instead of copying it because you want to do some OpenCL shit on it.

It is approx 137438953472 faster to copy 8 bytes then 1TB

I'll admit I'm no electrical engineer, but I would guess that like other companies cpu companies sacrifice performance for size in many areas.

>more speed
wrong

the size of the chip is a major limitation on processor speed because signals have further to travel.

>CPU
>SLI/Crossifre
>iGPU

AMD did it, and it was underwhelming as fuck, but they at least had their regular GPU line to back it up. Intel would legitimately need to come out with their own graphics cards, which would be fucking terrible because they would probably over-charge even more the nVidia does.

>Manly tears builds a pc

that doesn't mean more speed, it just means wider cores which will end up being underutilized.

> it just means wider cores

unless transistors are spent on cache. Then it actually would speed things up as cache misses are big bottlenecks for most applications.

Up to a point. Altho one has to wonder - what would happen if a cpu got 1gig of HBM instead of some useless IGP.

Intel has been talking about adding RAM directly on the same die for a long time. But it's still DRAM, so it's fucking high latency compared to what's in the cache. Yeah, you're cutting down latency on the bus by a few clocks but would that really matter much in the end? Bandwidth is not usually the bottleneck for 99% of CPU workloads.

>integrated graphic
>useless

I use it and actually like it. I don't play games much anymore, so it works great for it's purpose (light 3D but mostly video decoding)

Intel is just building an excuse to take over motherboard design. I'm sure with those 200 extra pins they added they can get about 7% more performance in threaded applications.

You could make that argument at just about every step in the design of processors since the 1980s. Back in the day the CPU was basically just an ALU. Since then it's absorbed more and more.

One of these days your computer is going to be a CPU you plug into a board with ports on it, but no other chips.

LGA 3647 is primarily for the new Xeon Phis that slot into motherboards and can self-boot. The new Xeon Phis have up to 72 cores.

Its primarily for the memory. Wouldn't it be nice if you could include some type of on die memory, that worked with photonics? That would cut the size of the chip exponentially.

>useless igpu
why is Sup Forums so opposed to power efficiency?

Power 8 actually has buffer chips inbetween RAM and the memory controller, which eat up a heafty 64W of power
anandtech.com/show/10435/assessing-ibms-power8-part-1/7
not necessarily, you can't arbitrarily make a cache larger without losing speed and more importantly latency
fgiesen.wordpress.com/2016/08/07/why-do-cpus-have-multiple-cache-levels/
you actually get faster CPUs if you make them smaller, because signal travel time is a massive factor that limits speed
Making interconnects work across distance is a huge pain in the ass and requires a ton of engineering to work.
Better to have 1 long link from Memory Controller to RAM than one from CPU to Memory Controller and one from Memory Controller to RAM

>desk analogies
>ctrl+f "NUMA" -- 0 matches

Oh boy. I'll just skip reading that unless you have a specific part you want to point out.

If you increase the sizes of private caches, yes you run into bottlenecks due to MESI snooping. Level 3 is shared so it doesn't need to worry about bus snooping. So a big level 3 is better than a small level 3 and closer DRAM. But there are more caches than just that. The pipeline has a lot of caches for decoded microcode and such, which are non-associative.

>better to have 1 long link from Memory Controller to RAM than one from CPU to Memory Controller and one from Memory Controller to RAM

The memory controller is already on the die now. Not sure what you're on about.

>Making interconnects work across distance is a huge pain in the ass and requires a ton of engineering to work.

Yes there are reasons to do it, but that's not what we were talking about here. Latency improvements isn't the main concern. Bandwidth and cost are.

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Not at all an important post.

isn't bandwidth is limited by quality of the connection, which is highly dependant on length? I mean by moving parts from mainboard to die you cut down on long interconnects, which makes things cheaper & faster
>The memory controller is already on the die now
Yes, by having the memory controller on die they have to worry less about the "rest of the cpu"->memory controller connection than if it's seperate on the mainboard

>faster

"Faster" is a poorly defined term. Latency and bandwidth are not. You'll improve bandwidth, but most programs don't need to move 10+ GB a second through memory, so it really doesn't matter to improve that. Waiting for read/write cycles on DRAM costs cycles (adds latency), which causes pipeline stalls which means fewer retired instructions/second which means programs that take longer to execute and waste CPU time. Ofc clever code can hide latency, working with with the processor's pre-fetch, but non-linear accesses patterns need to happen from time to time.

>a new wirus has inserted your computer
>thank you for calling windows support

The die wouldnt be bigger, all the things like cache and shit would be off the die.
Thats why the slotted cpus were so big

The issue with a modern slotted cpu would be the amount of contacts you could fit on it. Look at ram, 244 pin ram is fuckin long, even if we halved or quartered the size of the contacts, youre looking at a very small number compared to lga or pga

And off die cache may not be a good idea anyway, because then you'd have slow cache

CPUs aren't getting smaller to skimp on performance you braindead gamertard, you don't want a huge-ass, expensive, hot shitty die, there's a reason die shrinks are almost always superior to their predecessors in one way or another.

It's not about power, necessarily (though that is true), it's about capacitance and hence speed.

The -nm in the process name is the width of the polysilicon gate of the transistor. The larger the gate, the more capacitance it has, and the longer it takes for a signal to activate the gate. If you need it to operate faster, you need more current and hence more power.

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Kek'ed

sorry to inform but no it isnt: servethehome.com/big-sockets-look-intel-lga-3647/

Top kek

jej

>What's the advantage to Intel for making this instead of two separate CPUs?
NUMA - It is slow to access memory on another processor compared to memory directly connected to one. And virtualization environments are generally limited by RAM rather than processing power. And finally a lot of software is licensed by socket.

Aren't there still daughter boards in use for this kind of thing? A smaller pcb with an imc socket with ram slots on board as well, I mean a graphics card is pretty much that but all soldered.

So why don't they fucking implement the GCs that way?

Why don't they make bigger CPUs to fit more transistors?

power consumption

Heat, power consumption and after a certain point the CPU's frequency would need to be lowered because electrons wouldn't have enough time to travel along the chip's length between two cycles.

Why don't they just put 2 CPUs on top of one another

>heat, power consumption
Implying the end consumer cares about that
>after a certain point
but we aren't at that point are we?

it's big, but not really that much bigger than existing Xeon packages given the amount of IO it adds.

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*gives you an upvote*

SOCKET A YEAR

numa numa e

>SP4 and SP3 have less pins than LGA 3647 too

what's your sauce on this?
32c Naples was recently claimed to expose all 8 channel ECC DDR4 lanes and all 128 PCIe lanes, which gets you to nearly 3000 pins before you even add power, interconnect, and secondary IO.

Holy shit kek

MUH DICK

and all Sup Forums will do with it is play video games made for children

So Intel is adding more CPUs instead of "more cores"?

and all Sup Forums will do with it is shitpost and post images of their current desktop

>more heat spreading
just more heat