AMD SHITSTOMPS NOVIDEO AFTER SODOMIZING INTEL HOW CAN NVIDITS EVER RECOVER

VEGA CONFIRMED FASTER THAN SLI NVIDIA 1080 THE 1080TI ISN'T EVEN ON THE RADAR EVERYONE ON SUICIDE WATCH

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Oh, the shiposters arrived. Like clockwork.

It's completely true

How so? You don't know anything besides Vega having 8 shader engines.

I know it's 50% faster than a 1080ti

How so? It's no longer geometry bottlenecked, yet it's still *only* 13tflops card.

TFLOPs is irrelevant for gaming.

Might be power related. If anything, this tells us Vega is more power hungry than gp104/102, which quite honestly, I think everyone already expected.

They are, very much so.
Mods please delete this thread, it's pointless, everything meaningful related to Vega was discussed yesterday anyway.

You aren't putting a 300W part in a AIO Mac, so I doubt that.

>uses tiled binning and larger L2
>uses HBM
Honestly are you retarded or what?

We already know that Vega 10 is over 250w. In their marketing slides they showed it as under 300w.
Vega 10 is a competitor to the Titan X Pascal with a 250w tdp.
That depends on the clocks they're using, and how many CU are active.
They can sacrifice some clock speed to increase perf/watt, and Apple obviously won't be using the same binning as your average consumer parts. They'll get cherry picked cream of the crop for voltage per clock.

Crapple uses 56/64 CU Vega10's.

The apple part runs at 150MHz less, I doubt you'd end up with more than 10% performance from such a mild downclock, the previous AIO Mac GPU was a 140W part.

All we know is that the chip inside the iMac is Vega, nothing else. Fwiw it could be an underclocked, undervolted one, which wouldn't be surprising considering the type of chassis it will be into.

We know its flops, 11 tflop fp32, and apparently it's using the cut 56CU version of Vega so any lower clocks won't be even needed, for maximum power efficiency Apple could have gone with the 64CU with lower clocks(shaders are more efficient than clockspeeds), yet they didn't.

No, both 56 and 64 CU versions are available for new throttlemac pro.

>trust me I know better than multi billion company

...

Nvidia is fucking finished.

Wew really? Even Evergreen failed to kill nVidia.

It's a joke.
Actually more like a tradition, let me have my fun.

I wonder when will IBM buy NVIDIA.

>225W

After Polaris, I'll believe it when I see it. I remember AMD announcing ludicrous wattage numbers (some of

Polaris has similar perf/watt as Fiji, you don't find that strange at all?
AT ALL?

Bega has longer bibeline for higher optimal clocks.

What's strange with half-Fiji at 14nm doing the same as Fiji? GCN was intended to clock at ~800-900mhz top.

>Different archs have similar perf/watt

What are you trying to imply?

Neither Fiji nor Polaris are at optimal clocks, 14nm finfets alone bring a good reduction in power.
Polaris is a pipecleaner.

No, we don't know that it's 8 shader engines; that's speculation.

It's my belief that it is 4 and that youtuber misinterpreted that die layout in more ways than one.
I don't know why there is a gap in the CUs, but it's there. It could be because of how the wires run to work at an inside-out fashion for less latency.

That's what I said.
>Polaris is a pipecleaner
And a good one, just look at Zeppelin yields.

No, it literally means it has 8 shader engines. AMD themselves stated their new scheduler could operate with >4 shader engines.

>They are, very much so.
Mods please delete this thread, it's pointless, everything meaningful related to Vega was discussed yesterday anyway.

Mods please b& faggot for being faggot.
But not me because am not faggot like user, and op, but fuck you for thinking about b&ing me. Love you.

Pls b& everyone in thread.

They also literally said that Vega was 4 shader engines, fuck face.
If those are 8 shader engines, where are the matching geometry processors and ROP clusters for each, you ignorant twat who can only regurgitate shit you heard from a youtuber and who can't think for himself?

The improved load balancing slide implies 4+ engines, but it could also mean 4 engines but cut in half with each half having its own ROP/geometry units, which is technically similar

This. Shill thread evolving to people actually discussing tech? Sup Forums has gone mad I say

The mac versions are binned for efficiency. they're also only 11tflops so that means they're probably a couple hundred mhz downclocked for efficiency. don't expect consumer vega to be nearly as efficient.

>150mhz lower
>10% slower
>uses half the power

Yeah, I doubt that.

Where the fuck did they say about 4 shader engines you fuckwit?

Every-fucking-where, you fuckwit.
How about Anandtech? Fuck off.

A shader engine is more than just a group of CUs, you retards.
It's much more likely that they simply split the CUs into two groups per shader engine rather than it being 8 shader engines. From what I see on the die, that's what they've done. You dumb pieces of shits don't know how to interpret a die shot and are just regurgitating shit you don't understand from someone else. Fuck off, faggot.

It's not even a die shot you fucking faggot and
>anandtech
>official AMD source
My fucking god you're so fucking retarded.

>This. Shill thread evolving to people actually discussing tech? Sup Forums has gone mad I say

Yes. It actually took a turn for the better. Very confusing turn of events actually.

Of course it's not a die shot, it's a RENDER of the die shot and stylized using the actual die shot layout.

Well usual clock/watt graphs aren't linear. There's a point where small clock adjustments cause massive power draw differences. But this tells us either:
>1) Vega is still lower than that point, a clock reduction didn't lower power draw much, and Apple's cooling is a fucking miracle to handle all that inside an AiO
>2) Vega is clocked to the moon, and slightly lower clocks caused a massive drop in voltage, amps, and consequently power draw

Most probable one is maybe 2)

I think
>8 shader engines
is some kind of keyword.

You'd be surprised
Going from 3.4ghz (max all core turbo boost speed) to 2.6ghz (base clock) on my 2012 macbook pro brings the power consumption down from 45 watts to just 15
So 150mhz for half the power sounds about right

Fury x vs fury nano
>160 mhz higher clock
>100 watt higher tdp
You are wrong, friend.
Keep deluding yourself though. It'll make AMDs stock keep climbing and my wallet expanding.

Anandtech reported on what AMD told them at press conferences, you stupid shit.

Those very same new slides from 2 days ago say the geometry rendering performance per shader engine is 419% higher than the Fury X
If it's really 8 shader engines, that means it's 838% higher than Fury X. REALLY fucking unlikely.

I'm not going to argue with some ignorant little faggot who doesn't understand any of this for himself and just repeats what he heard from some nobody youtuber's (misguided) analysis.
If you were trying to argue this in person, I'd be choking you out on my cock instead, you worthless, ignorant little faggot.

Fury X and Fury nano aren't clocked near 1600MHz for that comparison to make sense

Then why the fuck would they split fucking shader engines? It makes even less sense than 8 shader engines you dumb mongoloid.

Well is wrong
It's a 50MHz difference between the R9 Nano and Fury X.

>wanting something explained to someone as ignorant as

You're clueless, shut the fuck up retard.

I think the example satisfies the point that small clock changes lead to large tdp changes when you reach the upper clock limit of the chip.

Kys nigger.

If the shadder array is really separated, what's that in the middle?

I believe the middle is the hardware scheduler, which is said to be a significant amount of the die (~10%?)
And I believe part of those in the middle are the geometry processors and ROP clusters (the 4 sets of 2 equal sized rectangles at the four corners of that cluster of various sized rectangles)
So it goes from those hardware schedulers and likely various L1 caches into the 4 geometry processors, into the ROPs, and then outwards into the CUs.

Dat Fiji

Just you wait Nvidia. Just you wait.

Same inward to outward arrangement as I described in which strongly implies it's 4 shader engines like the 4 you can see there, that just, for some reason, has a gap between them.

Fuck tech youtubers and fuck the fucks on Sup Forums who have no understanding but regurgitate what tech youtubers say.

>Machine-like, battle armor inspired design

more like they can only fit one watercooled vega card in that case

Should be mostly right.
Tell me if anything's wrong.

where'd you find that die shot?
for ages the best thing floating around was crappy pic related:

flickr.com/photos/130561288@N04/29575201691/in/album-72157650403404920/

I think those aren't all ACEs, but is mostly correct.

...

I'd replace the L1 with the display controllers and the IF/GMI one with fixed function hardware like DSPs, VCE and UVD

> flickr.com/photos/130561288@N04/
you're my fucking hero, user, thanks.

looking at the way polaris is diced up, I'd say your shit is more than slightly fucked up.

> GCP/ACEs/HWSs are all believed to be in the center column, and ACEs aren't nearly that big
> front-end fixed-function units are also still probably in middle, between GCP and SEs
> L1 is spread out in tiny 16kB pieces per CU
> L2 was adjacent to RBEs, but that might change since they're getting coherent L1s now, what you have listed as front-end may be the new L2 location
> the new "HBCC" is probably a huge tag CAM for using part of the HBM as an associative n-way cache, which would probably fit in your red or light green boxes

all caps op should be auto ban

>Expecting good thermal design from the makers of throttlebook featuring 0.8Ghz

...

Holy fuck everything you listed is wrong.

What you have listed as ROPs is likely things like L1 cache, vector data stores, etc, for each CU. If it was rops, that's 192 of them when it has 62 and they aren't that alrge, you tard.
And the left is likely global data store. If it was a second L2 it'd be the same size as the right one.
What you ahve listed as "front end geometry units" is the memory controllers.
What you have listed as L1... what the fuck you have no idea how L1 works.
What you have listed as IF/GMI are hardware accelerators.
The only thing you MAYBE got right are the ACE.

I was going off this and the other Fiji diagrams.

That is not representative of how the Fiji die is actually laid out, dude.

functional diagram != layout, friendo

Nobody was actually kind enough to disect the Fiji floorpan before though.

anybody who can identify recurrent shapes, count, and read a functional diagram should be able to reach analysis along these lines:
> 16 PCIe PHY lanes, 256b DDR4 PHY lanes, 6 display controllers, ...

we'll see what comes of Vega, but simulated stuff like
is notoriously misleading about relative component sizes and placement.

idk dude it should be fairly obvious for many parts without labels.

"front ends" = geometry processors and ROPs, I think. Same that I think it is there on that Vega die render as I mentioned earlier.
And yeah, HWSs in the middle. Not sure about ACEs.

Shouldn't ACEs naturally be hanging off the scheduler/command processor? I mean their entire damn function is balancing compute and graphics and you don't do that without the scheduler

front-end is geometry/tessellation and rasterizers

R(asterizer)O(ut)P(ut)s = R(asterizer)B(and)E(nd) constituents are back end of the pipe

ROPs are the back end, user.

Vega 11.. 40-44CU?

Should be close enough to fight off the inevitable 2070(which should be right near a 1080 or slightly better)

Yeah, that's right, actually. Command processor (aka HWs), ACE, geometry processor, and ROPs should all be grouped together, and in that center area both for Fiji there and the Vega render.
But I can't figure out what those skinny rectangles to the tops and bottoms of the CUs are supposed to be, then, on the Vega render.

Almost surely 28-36 CUs for Vega 11. Vega 11 is the RX600 series.

>inb4 some retards asks about
>"but what about 1070 competitor!!!!"
>when the 1070 is shitty price/performance and has shitty use cases.
>1070 is artificial marketing bullshit and almost always a bad buy

ROPs and rasterizers are backend functions, they are in the CUs, ACE/HWS/geounits are not, they're in the frontend.

no they aren't.

see
Clear distinction between CU and CMD processor and what goes in what.

Why would something that needs to wait on the other units and is basically the last part of the pipeline be in the frontend?

They are side by side, not in line.
CUs go back and forth between the processors/schedulers. Thus it's best to place the ROPs by the processors/schedulers.
Sheesh.

Poor Volta.

I'm talking about the GPU pipeline, in short the ROPs are the last stage of the pipeline, just before the display I/O

Interconnects, L2 cache and random logic, most likely.

>*only* 13tflops
Titan Xp in 11 TFLOPS.

It's a shitload more when it boosts.

Tflops are just clockspeed*ALU count, they take into account basically nothing coming from drivers, APIs, geometry units, scheduling, caches and so on and so fort.

>It's a shitload more when it boosts.
Yeah, like 12 TFLOPS.
>when it boosts

Well aware, I just thought the comparison was stupid since Vega does have more grunt than literally any nVidia GPU in terms of raw FLOPS.

Who here is of the opinion AMD is slightly delaying Vega because they're taking time to do some better voltage binning instead of dumping GPUs in the market with 5-30% different power draw differences at the same performance

>No, we don't know that it's 8 shader engines; that's speculation.
Thank you, I came here to say this.

TitanXP can boost in _muhgayms_ close to 1800MHz at stock.
It's marketed boost clock is far below that.