Intel BTFO

Intel BTFO

Other urls found in this thread:

theregister.co.uk/2016/09/09/intel_soft_machines/
youtube.com/watch?v=Qu6nWu22YQg
youtu.be/Qu6nWu22YQg
twitter.com/NSFWRedditVideo

how does it compare with the first gen?

No way that's real.

It's probably fake and gay.

>mp ratio: 7.28
>6 cores
what the fuck

PST CONFIRMED

Source?

>MUTLI-THREADING
>MUTLI
Confirmed fake and gay.

>mutli-threading
okay

The fuck

I wish it's real but I guess that is not possible

>SMT
>wtf?

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>2 cores for one thread
That's not how it works you dumb shit.

Well it's not how HT or smt work but that does not mean that it is not possible to use another core(not thread) to boost single core performance.

It might be fake, but I'm sure that it is possible to improve single core performance by using 2 codes to run a single process. This could for example improve branch prediction: Both cores choose different options and the only guessing right can continue while the second one ist copying the data from core one. Some things like that are theoretical possible.

>but that does not mean that it is not possible to use another core(not thread) to boost single core performance.
That's exactly what it means. Independent parts of code are already boosted by out of order execution, parts that depend on each other can't be boosted PERIOD.

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You know what branch prediction is? As I stated above it might be possible to improve branch prediction by using two cores. The code is still executed in the correct order, but the processor has an improved branch prediction rate while sacrificing a whole core that cannot be used for other purposes while this method is applied. This is not just executing unrelated code on another core but constantly using a second core all the time to make two guesses instead of one every time branch prediction needs to be done. Depending on the workload this can boost performance.

Branching is not the only way parts of code may depend on each other.

hahahahhahahahahahahah this is intels defence? hahahahah

Never said that, but if you execute your code in the correct order false branch prediction can decrease performance by quite a bit. If you could further decrease the probability of this case you could improve performance.

>Friendly reminder to never pay attention to prerelease benchmarks.

That's not even close to +50% like the pic claims.

Branch prediction is already over 90% for new AMD and Intel architectures.

>Muh $2k housefire i9

Well I don't claim it is the explanation, I just state that using 2 cores for one thread can boost performance.

Intel BTFO

>250cb
INTEL BTFO AGAIN. HAHAHAHA

I don't think it would help much. Zen is already 6 issue. Two cores operating on one thread would be 12 issue and there isn't that much instruction level parallelism in most workloads.

>cpuid with retail name instead of ES code
Probably fake.

I really want this to be true. It would be fucking hilarious.

Well that depends on the workload, doesn't it? :)

If the code represents just a common if condition, then there are just two possible outcomes: true or false. By using two cores we can predict both cases. Normally we would have something like ( you said) a 90% Chance of guessing correct => 10% Chance of guessing wrong and using maybe dozens of cpu cycles just to refill the pipeline, while with two cores we might need one cycle to copy the pipeline from one core to another. Of course there are predictions with more than 2 branches which still can be guessed wrong but in that case normal or two core makes no difference, while the chances to guess correct are improved.

I don't really understand what you are saying. What do you mean with 6 issue? English is not my native language.

And like I said it would not need instruction level paralism, just branch prediction which is used every time if, else, switch statements and loops are used. Anytime there might be a decision which code has to be executed next will be guessed to fill the pipeline more efficiently, but guessing can be wrong. Guessing two times improves this.

>That tweet.
>Liked by a bunch of pajeets

>6C/12T
Weren't they supposed to be 12C/24T according to """leak""" released a week ago?

It's only as good as 100% branch prediction.

Yes please, I want to see more hilarious slides like pic related.

The best explanation (assuming the numbers are legit) I can think of is that they found free space in the 12nm transition and decided to widen the AVX implementation which turned out easier than expected so they rolled with it.

Likely a stutter fest in
MUH GAYMENS

Which would be completely terrible, am I right? :)

Like I said, depending on the workload this could have an enormous impact. Imagine a code where every fifth instruction is such a branch prediction. Normally you would wait on 10% of all cases for dozens of cycles (well i don't know the numbers, but modern pipelines have a lot of states as far as I know). Now you would wait for one cycle two copy the data from core to core.

Well you know the 1920X? That one might have an successor too......

>Which would be completely terrible,
Yes. 10% on branching only, at most. Like 1% in general workloads. And you trade an entire for that. If that's not fucking terrible I don't know what is.

If this is true I would be more exited to see if they can manage to provide a hybrid mode, like running the main game loop process on such a two core bundle while using the other cores normal to provide maximum performance.

Literally impossible

t. armchair hardware expert

>that blur on the 2 in CPU-Z
You tried

theregister.co.uk/2016/09/09/intel_soft_machines/

youtube.com/watch?v=Qu6nWu22YQg

Let's say 1%. Let's say it saves us 25 Cycles of pipelining. Normally I could execute 75 Instructions in 100 Cycles, now I could do 100 in 100. 100/75 =: 1.33, so 33% more performance. Let's say the shown synthetic benchmarks are have a 2% Chance of an instruction involving a false branch prediction: 50 instructions per 100 cycles => we already have a 2x performance. I know these numbers are just estimates but given the workload depends on many branch prediction a big improvement can be made.

Ouch, just noticed thatm the 2 is touching the 6 and lower than the other numbers. Also explains why the took a picture of the screen, to distort it to make it more difficult to see the poor editing

Keep the context in mind. It's supposed to represent a marketing slide. Exact definition of a "thread" unknown.
What if by thread they mean SMT-split-responsible silicon pathways? Technically possible, although still fake, as fake as OP.

OP here. Thanks for playing.

it doesn't really need all those cores if it has that level of performance improvement on similar core counts

>mutli

Did the pajeets at wccf say that?

Reservation statuons from one physical thread are prolly lended to the other physical thread.
Double the size of your tomasulo resources and you'll stall way less.
Double the performance? No... But more performance for sure.

well, it's 50% performance, not 100%

youtu.be/Qu6nWu22YQg

8.08 ratio maddafakka

probably i7-8700k

I dunno, striping instructions and cache across multiple cores is as lusty as it sounds, but i don't think anyone would waste their time believing this is real

>ITT: butt blasted pajeets attempt more shilling
move over intel, you had your time in the sun and now you're dessicated

It's like a religion, you need to have faith and prey for a miracle.

>tfw Waited

>As I stated above it might be possible to improve branch prediction by using two cores.
lol. If you don't have any idea how shit works, stop speculating in public.

Branch prediction needs ridiculously low latency, or the entire point of it is defeated. If you're having branch-prediction data trickling through the entire pipeline, you'd be better off without it altogether.

Yeah, if it just weren't for that, I'd have believed it entirely.

>English is not my native language.
More like processor architecture isn't your native language.

Here's a little something you can start reading from:

>one cycle to copy the pipeline from one core to another
If you had the silicon technology to do that, you could sell it to any CPU company for a billion dollars.

10.82
GET ON MY LEVEL NERDS

what cock rate

>curved meme monitor

Jesus christ this shit needs to die.

>677.9 CPU-Z / 250 CB Single
that'd be crazy

Memes xD

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CUT MY LIFE TO PIECES

>windows 8

BUT MUH COFEEEEE LAKE ITS NOT FAIR

two massive leaps in a row?
this doesn't sound like AMD. Seems fake.

daily reminder that this is the kind of dumbshit who regularly participates in AMD/Intel fanboy war threads and this shit should be eradicated from the board

corporate cock sucking and gamertardism is not technology

a) it wouldn't be single core performance you infant

b) the two cores would have to ensure their registers stay in sync as they'd be using THE SAME FUCKING CONTEXT

c) if this was a good idea in any aspect, why wouldn't AMD simply make a 4-way superscalar pipeline with double the hardware in each core instead of this retarded notion?

>still no source

>why wouldn't AMD simply make a 4-way superscalar pipeline with double the hardware in each core instead
because making a bentium 4 v2.0 would accomplish nothing

That's pitiful.

wow

it's from a youtube video

It was posted around yesterday and immediately called out by everyone.

Nobody believes it's real except the fanboyist of fanboys

Well im sure you know how a transistor works. Just set one bit to 1, read the data from one pipeline, copy it to another. The basic concept is not that hard. Of course this would need a couple of connections from core 1 to core 2.

Goddamit Intel.

Not bad, looks like single thread has increased some on the 8th gen.

Nobody will believe that without some salsa OP.

>a couple of connections
That's putting it mildly, yes. Also those connections are long enough to have an impedance that's very guaranteed to make the transfer delay longer than one clock cycle. Not to mention all the data registers in every data structure in every core would suddenly have to be dual-ported.

Intel absolutely BLOWN THE FUCK OUT!

Well no not all data registers, just every data register used for pipelining. The context of the processors would stay the same, both calculated the same result, but one has already the next instructions loaded in the pipeline, the other one has to copy them. In the designing process the manufacturer would have to place the pipelines of two cores in a close distance to another so that a data transfer would be possible in one cycle.

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